Xilinx SelectIO 7 Series - IDDR VHDL and Verilog Templates

112 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 2: SelectIO Logic Resources
IDDR VHDL and Verilog Templates
The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL
and Verilog.
S/R
(1)
Set/Reset Synchronous/Asynchronous Set/Reset pin. S/R is
asserted High.
Notes:
1. The IDDR primitive contains both set and reset pins. However only one can be used per IDDR. As a
result, S/R is described instead of separate set and reset pins.
Table 2-2: IDDR Attributes
Attribute Name Description Possible Values
DDR_CLK_EDGE Sets the IDDR mode of operation
with respect to clock edge
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
INIT_Q1 Sets the initial value for Q1 port 0 (default), 1
INIT_Q2 Sets the initial value for Q2 port 0 (default), 1
SRTYPE Set/Reset type with respect to
clock (C)
ASYNC (default), SYNC
Table 2-1: IDDR Port Signals (Cont’d)
Port
Name
Function Description
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