7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 119
UG471 (v1.10) May 8, 2018
Input Delay Resources (IDELAY)
IDELAY Attributes
Table 2-5 summarizes the IDELAY attributes.
Table 2-5: IDELAY Attribute Summary
Attribute Value Default Value Description
IDELAY_TYPE String: FIXED,
VARIABLE,
VAR_LOAD, or
VAR_LOAD_PIPE
FIXED Sets the type of tap delay line. FIXED
delay sets a static delay value.
VAR_LOAD dynamically loads tap
values. VARIABLE delay dynamically
adjusts the delay value.
VAR_LOAD_PIPE is similar to
VAR_LOAD mode with the ability to
store the CNTVALUEIN value ready for
a future update.
DELAY_SRC String: IDATAIN,
DATAIN
IDATAIN IDATAIN: IDELAY chain input is
IDATAIN
DATAIN: IDELAY chain input is
DATAIN
IDELAY_VALUE Integer: 0 to 31 0 Specifies the fixed number of delay taps
in fixed mode or the initial starting
number of taps in VARIABLE mode
(input path). When IDELAY_TYPE is set
to VAR_LOAD, or VAR_LOAD_PIPE
mode, this value is ignored and assumed
to be zero.
HIGH_PERFORMANCE_MODE
Boolean: FALSE or TRUE TRUE When TRUE, this attribute reduces the
output jitter. The difference in power
consumption is quantified in the Xilinx
Power Estimator tool.
SIGNAL_PATTERN String: DATA, CLOCK DATA Causes the timing analyzer to account for
the appropriate amount of delay-chain
jitter in the data or clock path.
REFCLK_FREQUENCY Real: 190 to 210,
290 to 310, or 390 to 410
200 Sets the tap value (in MHz) used by the
timing analyzer for static timing analysis.
The ranges of 290.0 to 310.0 and 390 to
410 are not available in all speed grades.
See the 7 series FPGA data sheets.
CINVCTRL_SEL Boolean: FALSE or TRUE FALSE Enables the CINVCTRL_SEL pin to
dynamically switch the polarity of the C
pin.
PIPE_SEL Boolean: FALSE or TRUE FALSE Selects pipeline mode. This attribute
should only be set to TRUE when using
the VAR_LOAD_PIPE mode of
operation.
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