14 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
New Features
The 7 series devices support many of the same features supported in the Virtex®-6 and
Spartan®-6 FPGAs, however, some of these features are changed in form or functionality.
These changes include:
• There are now two distinctly different types of I/O banks, HR and HP, and each type
supports some unique I/O standards and features.
• The memory interface related I/O standards such as SSTL and HSTL now support the
SLEW attribute, and are selectable between both FAST and SLOW edge rates. The
default SLEW for all I/O standards is SLOW, which has been the case for all I/O
standards that supported the SLEW attribute in all previous FPGA families (namely
LVCMOS and LVTTL). However, because this attribute is a new addition to the
memory interface standards, if left unchanged (not specified in the RTL, UCF file, or
I/O planning software), the default slew rates for these for these standards will result
in much slower slew rates than in previous families. To achieve similar slew rates as in
previous families, new designs now require the SLEW attribute to be specified and set
to FAST. Table 1-56 shows (among other features) which I/O standards support the
SLEW attribute.
• The 7 series FPGA DCI calibration circuit has improved the accuracy of the internal
termination resistance. As a result, the selection of values for the external precision
resistors is different for the split-termination DCI standards. Specifically, the external
resistors are now chosen to be double the target Thevenin-equivalent resistance,
whereas in Virtex-6 FPGAs and earlier families they were chosen to be equal to the
target Thevenin-equivalent resistance. See the Xilinx DCI section for more details.
• There are additional I/O Logic design primitives with new features and functions. See
Chapter 2, SelectIO Logic Resources for more details on these primitives.
Internal differential termination (DIFF_TERM) Supported Supported
IDELAY Supported Supported
ODELAY Supported N/A
IDELAYCTRL Supported Supported
ISERDES Supported Supported
OSERDES Supported Supported
ZHOLD_DELAY N/A Supported
Notes:
1. Not all I/O standards and drive strengths are supported in both the HP and HR I/O banks. The I/O
Bank Availability column in Table 1-55 shows the specific I/O standards that are available in the HP
and HR I/O banks.
2. Although LVDS is generally considered a 2.5V I/O standard, it is supported in both the HR and HP
I/O banks.
Table 1-1: Supported Features in the HR and HP I/O Banks (Cont’d)
Feature HP I/O Banks HR I/O Banks
To Next Page
Loading...
Need help?
General
