Xilinx SelectIO 7 Series - Page 98

98 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Table 1-55, summarizes the V
CCO
and V
REF
requirements for each 7 series FPGA
supported I/O standard. For more detailed DC specifications, including the recommended
operating ranges of the supplies for each supported I/O standard, see the 7 series FPGA
data sheets.
Table 1-55: V
CCO
and V
REF
Requirements for Each Supported I/O Standard
I/O Standard
I/O Bank
Availability
V
CCO
(V) V
REF
(V)
Output Input
Input with
DIFF_TERM = TRUE
Input
BLVDS_25 HR 2.5 2.5
(1)
N/A N/A
DIFF_HSTL_I Both 1.5 Any N/A N/A
DIFF_HSTL_I_18 Both 1.8 Any N/A N/A
DIFF_HSTL_I_DCI HP 1.5 1.5 N/A N/A
DIFF_HSTL_I_DCI_18 HP 1.8 1.8 N/A N/A
DIFF_HSTL_II Both 1.5 Any N/A N/A
DIFF_HSTL_II_18 Both 1.8 Any N/A N/A
DIFF_HSTL_II_DCI HP 1.5 1.5 N/A N/A
DIFF_HSTL_II_DCI_18 HP 1.8 1.8 N/A N/A
DIFF_HSTL_II_T_DCI HP 1.5 1.5 N/A N/A
DIFF_HSTL_II_T_DCI_18 HP 1.8 1.8 N/A N/A
DIFF_HSUL_12 Both 1.2 Any N/A N/A
DIFF_HSUL_12_DCI HP 1.2 1.2 N/A N/A
DIFF_MOBILE_DDR HR 1.8 1.8 N/A N/A
DIFF_SSTL12 HP 1.2 Any N/A N/A
DIFF_SSTL12_DCI HP 1.2 1.2 N/A N/A
DIFF_SSTL12_T_DCI HP 1.2 1.2 N/A N/A
DIFF_SSTL135 Both 1.35 Any N/A N/A
DIFF_SSTL135_R HR 1.35 Any N/A N/A
DIFF_SSTL135_DCI HP 1.35 1.35 N/A N/A
DIFF_SSTL135_T_DCI HP 1.35 1.35 N/A N/A
DIFF_SSTL15 Both 1.5 Any N/A N/A
DIFF_SSTL15_R HR 1.5 Any N/A N/A
DIFF_SSTL15_DCI HP 1.5 1.5 N/A N/A
DIFF_SSTL15_T_DCI HP 1.5 1.5 N/A N/A
DIFF_SSTL18_I Both 1.8 Any N/A N/A
DIFF_SSTL18_I_DCI HP 1.8 1.8 N/A N/A
DIFF_SSTL18_II Both 1.8 Any N/A N/A
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