Xilinx SelectIO 7 Series - Differential HSUL_12

86 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Figure 1-65 shows a sample circuit illustrating a bidirectional board topology (with no
termination) for HSUL_12. Only HP I/O banks support the DCI version.
Differential HSUL_12
Figure 1-66 shows a sample circuit illustrating a board topology (with no termination) for
differential HSUL_12 with unidirectional signalling.
X-Ref Target - Figure 1-65
Figure 1-65: HSUL_12 with Bidirectional Signalling
Z
0
IOB
HSUL_12
ug471_c1_55_011811
Z
0
IOB
IOB
HSUL_12_DCI
HSUL_12_DCI
V
REF
= 0.60V
+
–
V
REF
= 0.60V
+
–
External Termination
DCI
IOB
HSUL_12
R
0
= 50Ω
V
REF
= 0.60V
V
REF
= 0.60V
R
0
= 50Ω
X-Ref Target - Figure 1-66
Figure 1-66: Differential HSUL_12 with Unidirectional Signalling
ug471_c1_56_011811
+
–
External Termination
Z
0
IOB
IOB
DIFF_HSUL_2
DIFF_HSUL_2
Z
0
DIFF_HSUL_2
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