Xilinx SelectIO 7 Series - Differential SSTL18, SSTL15, SSTL135, SSTL12

80 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Differential SSTL18, SSTL15, SSTL135, SSTL12
Figure 1-59 shows a sample circuit illustrating a termination technique for differential
SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional termination. In a specific circuit,
all drivers and receivers must be at the same voltage level (1.8V, 1.5V,1.35V, or 1.2V); they
are not interchangeable.
X-Ref Target - Figure 1-59
Figure 1-59: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination
UG471_c1_49_042913
+
–
External Termination
Z
0
IOB
IOB
DIFF_SSTL18_(I/II)
DIFF_SSTL15(_R)
DIFF_SSTL135(_R)
DIFF_SSTL12
DIFF_SSTL18_(I/II)
DIFF_SSTL15(_R)
DIFF_SSTL135(_R)
DIFF_SSTL12
DIFF_SSTL18_(I/II)
DIFF_SSTL15(_R)
DIFF_SSTL135(_R)
DIFF_SSTL12
Z
0
50Ω
50Ω
V
TT
=
0.9V for DIFF_SSTL18_(I/II)
0.75V for DIFF_SSTL15(_R)
0.675V for DIFF_SSTL135(_R)
0.6V for DIFF_SSTL12
V
TT
=
0.9V for DIFF_SSTL18_(I/II)
0.75V for DIFF_SSTL15(_R)
0.675V for DIFF_SSTL135(_R)
0.6V for DIFF_SSTL12
V
TT
=
0.9V for DIFF_SSTL18_II
V
TT
=
0.9V for DIFF_SSTL18_II
50Ω
50Ω
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