Xilinx SelectIO 7 Series - SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination; HSUL_12 (High Speed Unterminated Logic); HSUL_12 and DIFF_HSUL_12

84 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination
Figure 1-63 shows a sample circuit illustrating a termination technique for SSTL18,
SSTL15, SSTL135, or SSTL12 (T_DCI) with on-chip split-thevenin termination. In this
bidirectional I/O standard, when 3-stated, the internal split-termination is invoked on the
receiver and not on the driver.
HSUL_12 (High Speed Unterminated Logic)
The HSUL_12 standard is for LPDDR2 memory buses. HSUL_12 is defined by the JEDEC
standard JESD8-22. 7 series FPGAs support this standard for single-ended signaling and
differential signaling. Similar to SSTL, this standard also requires a differential amplifier
input buffer and a push-pull output buffer.
HSUL_12 and DIFF_HSUL_12
The differential (DIFF_) version uses complementary single-ended drivers for outputs and
differential receivers for inputs.
X-Ref Target - Figure 1-63
Figure 1-63: SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination
ug471_c1_53_021214
Z
0
IOB
IOB
1
0
SSTL18_II_T_DCI
SSTL15_T_DCI
SSTL135_T_DCI
SSTL12_T_DCI
SSTL18_II_T_DCI
SSTL15_T_DCI
SSTL135_T_DCI
SSTL12_T_DCI
V
CCO
=
1.8V for SSTL18_II_T_DCI
1.5V for SSTL15_T_DCI
1.35V for SSTL135_T_DCI
1.2V for SSTL12_T_DCI
R
VRN
=
2Z
0
= 100Ω
R
VRP
=
2Z
0
= 100Ω
V
REF
=
0.9V for SSTL18_II_T_DCI
0.75V for SSTL15_T_DCI
0.675V for SSTL135_T_DCI
0.6V for SSTL12_T_DCI
V
REF
=
0.9V for SSTL18_II_T_DCI
0.75V for SSTL15_T_DCI
0.675V for SSTL135_T_DCI
0.6V for SSTL12_T_DCI
+
–
DCI
Not 3-stated (T pin logic Low)
3-stated (T pin logic High)
Table 1-37: Available I/O Bank Type
HR HP
Available Available
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