50 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
• DIFF_TERM = FALSE (Default)
The DIFF_TERM attribute uses the following syntax in the UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME> DIFF_TERM = "[TRUE|FALSE]";
Internal V
REF
The V
REF
for an I/O bank can be (optionally) generated inside the 7 series FPGA. Internal
generation removes the need to provide for a particular V
REF
supply rail on the printed
circuit board (PCB) and frees the multi-purpose V
REF
pins in a given I/O bank to be used
as normal I/O pins. Consider this alternative when the 7 series FPGA is the only device on
the board/system requiring a particular V
REF
voltage supply level, or if there is a shortage
of I/O pins in a given I/O bank. The internally generated V
REF
(INTERNAL_VREF) is
sourced from the V
CCAUX
. Each bank has a single V
REF
plane and each I/O bank can
therefore only have the optional INTERNAL_VREF set to a single voltage level for the
entire bank.
The constraint INTERNAL_VREF is assigned to one bank at time.
Example 1: INTERNAL_VREF for Bank 14 using HSTL_II (1.5V), which requires a 0.75V
reference voltage, uses the following constraint:
INTERNAL_VREF_BANK14 = 0.75;
Example 2: INTERNAL_VREF for Bank 15 using HSTL_II_18 (1.8V), which requires a 0.9V
reference voltage, uses the following constraint.
INTERNAL_VREF_BANK15 = 0.90;
The rules for using INTERNAL_VREF are:
•One value of V
REF
can be set for the bank.
• INTERNAL_VREF can only be set to the nominal reference voltage value of a given
I/O standard.
• Valid settings of INTERNAL_VREF are:
•0.60
• 0.675
•0.75
•0.90
• When using INTERNAL_VREF in a bank, the multi-purpose V
REF
pins in that bank
can be used as normal I/O.
The rules for combining I/O standards in the same bank also apply for INTERNAL_VREF.
VCCAUX_IO Constraint
VCCAUX_IO is a constraint available for I/O nets and primitives that should be specified
in the design if the V
CCAUX_IO
pins for any HP banks are going to be set to 2.0V.
VCCAUX_IO defaults to a value of DONTCARE but can be set to NORMAL (1.8V) or
HIGH (2.0V). If the V
CCAUX_IO
pins in a given bank are to be powered at 2.0V, at least one
I/O net or primitive in that bank should have its VCCAUX_IO constraint set to HIGH, and
all other I/O nets and primitives that must either be set to HIGH or DONTCARE. If the
V
CCAUX_IO
pins in a bank are to be powered at 1.8V, at least one I/O net or primitive in that
bank should have this constraint set to NORMAL, and all other I/O nets or primitives
should be set to either NORMAL or DONTCARE.
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