Xilinx SelectIO 7 Series User Manual

26 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Split-Termination DCI (Thevenin Equivalent Termination to V
CCO
/2)
Some I/O standards (e.g., HSTL and SSTL) require an input termination resistance (R) to a
V
TT
voltage of V
CCO
/2 (see Figure 1-10).
Split-termination DCI creates a Thevenin equivalent circuit using two resistors of twice the
resistance value (2R). One terminates to V
CCO
, the other to ground. Split-termination DCI
provides an equivalent termination to V
CCO
/2 using this method. The 2R termination
resistance is set by the external reference resistors. For example, to achieve the Thevenin
equivalent parallel-termination circuit of 50Ω to V
CCO
/2, would require 100Ω external
precision resistors at the VRN and VRP pins. The DCI input standards supporting split
termination are shown in Table 1-2.
X-Ref Target - Figure 1-1 0
Figure 1-10: Input Termination to V
CCO
/2 without DCI
R
UG471_c1_12_011811
V
CCO
/2
V
REF
IOB
Z
0
7 Series FPGA
Table 1-2: All DCI I/O Standards Supporting Split-Termination DCI
HSTL_I_DCI DIFF_HSTL_I_DCI SSTL18_I_DCI DIFF_SSTL18_I_DCI
HSTL_I_DCI_18 DIFF_HSTL_I_DCI_18 SSTL18_II_DCI DIFF_SSTL18_II_DCI
HSTL_II_DCI DIFF_HSTL_II_DCI SSTL18_II_T_DCI DIFF_SSTL18_II_T_DCI
HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL15_DCI DIFF_SSTL15_DCI
HSTL_II_T_DCI DIFF_HSTL_II_T_DCI SSTL15_T_DCI DIFF_SSTL15_T_DCI
HSTL_II_T_DCI_18 DIFF_HSTL_II_T_DCI_18 SSTL135_DCI DIFF_SSTL135_DCI
SSTL135_T_DCI DIFF_SSTL135_T_DCI
SSTL12_DCI DIFF_SSTL12_DCI
SSTL12_T_DCI DIFF_SSTL12_T_DCI
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English