Xilinx SelectIO 7 Series - IDELAYE2 Primitive

116 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 2: SelectIO Logic Resources
IDELAYE2 Primitive
Figure 2-11 shows the IDELAYE2 primitive.
Table 2-4 lists the available ports in the IDELAYE2 primitive.
X-Ref Target - Figure 2-1 1
Figure 2-11: IDELAYE2 Primitive
C DATAOUT
INC
CE
IDATAIN
REGRST
LD
CINVCTRL
CNTVALUEIN[4:0]
LDPIPEEN
DATAIN
CNTVALUEOUT[4:0]
IDELAYE2
ug471_c2_09_011911
Table 2-4: IDELAYE2 Primitive Ports
Port Name Direction Width Function
C Input 1 Clock input used in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
REGRST Input 1 Reset for the pipeline register. Only used in VAR_LOAD_PIPE mode.
LD Input 1
Loads the IDELAYE2 primitive to the pre-programmed value in VARIABLE
mode. In VAR_LOAD mode, it loads the value of CNTVALUEIN.
In VAR_LOAD_PIPE mode it loads the value currently in the pipeline register.
CE Input 1 Enable increment/decrement function.
INC Input 1 Increment/decrement number of tap delays.
CINVCTRL Input 1 Dynamically inverts the clock (C) polarity.
CNTVALUEIN Input 5 Counter value from FPGA logic for dynamically loadable tap value.
IDATAIN Input 1 Data input for IDELAY from the IBUF.
DATAIN Input 1 Data input for IDELAY from the FPGA logic.
LDPIPEEN Input 1
Enables the pipeline register to load data.
DATAOUT Output 1 Delayed data from one of two data input ports (IDATAIN or DATAIN).
CNTVALUEOUT Output 5 Counter value going to FPGA logic for monitoring tap value.
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