Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 145
UG471 (v1.10) May 8, 2018
Input Serial-to-Parallel Logic Resources (ISERDESE2)
ISERDESE2 Primitive (ISERDESE2)
The ISERDESE2 primitive in 7 series devices (shown in Figure 3-2) is ISERDESE2.
Table 3-1 lists the available ports in the ISERDESE2 primitive.
X-Ref Target - Figure 3-2
Figure 3-2: ISERDESE2 Primitive
UG471_c3_02_090810
BITSLIP
CE1
CE2
CLK
CLKB
OCLK
OCLKB
CLKDIVP
CLKDIV
DYNCLKSEL
DYNCLKDIVSEL
SHIFTIN1
SHIFTIN2
RST
D
DDLY
OFB
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SHIFTOUT1
SHIFTOUT2
O
ISERDESE2
Primitive
Table 3-1: ISERDESE2 Port List and Definitions
Port Name Type Width Description
Q1 – Q8 Output 1 (each) Registered outputs. See Registered Outputs – Q1 to Q8.
O Output 1 Combinatorial output. See Combinatorial Output – O.
SHIFTOUT1 Output 1 Carry out for data width expansion. Connect to SHIFTIN1 of slave IOB. See
ISERDESE2 Width Expansion.
SHIFTOUT2 Output 1 Carry out for data width expansion. Connect to SHIFTIN2 of slave IOB. See
ISERDESE2 Width Expansion.
D Input 1 Serial input data from IOB. See Serial Input Data from IOB - D.
DDLY Input 1 Serial input data from IDELAYE2. See Serial Input Data from IDELAYE2 -
DDLY.
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English