7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 39
UG471 (v1.10) May 8, 2018
7 Series FPGA SelectIO Primitives
IBUFDISABLE port that can be used to disable the input buffer during periods that the
buffer is not being used. The IBUFDS_DIFF_OUT_INTERMDISABLE primitive also has an
INTERMDISABLE port that can be used to disable the optional uncalibrated
split-termination feature. See Uncalibrated Split Termination in High-Range I/O Banks
(IN_TERM) for more details on this feature.
The IBUFDS_DIFF_OUT_INTERMDISABLE primitive can disable the input buffer and
force both the O and OB outputs to the fabric High when the USE_IBUFDISABLE attribute
is set to TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set
to FALSE, the IBUFDISABLE input is ignored and should be tied to ground. If the I/O is
using the optional uncalibrated split-termination feature (IN_TERM), this primitive
disables the termination legs whenever the INTERMDISABLE signal is asserted High.
These features can both be combined to reduce power whenever the input is idle.
IOBUF
The IOBUF primitive is needed when bidirectional signals require both an input buffer and
a 3-state output buffer with an active High 3-state T pin. Figure 1-24 shows a generic
7 series FPGA IOBUF. A logic High on the T pin disables the output buffer.
IOBUF_DCIEN
The IOBUF_DCIEN primitive shown in Figure 1-25 is available in the HP I/O banks. It has
an IBUFDISABLE port that can be used to disable the input buffer during periods that the
buffer is not being used. The IOBUF_DCIEN primitive also has a DCITERMDISABLE port
that can be used to manually disable the optional DCI split-termination feature. See
X-Ref Target - Figure 1-2 3
Figure 1-23: Differential Input Buffer With Input Buffer Disable and IN_TERM
Disable (IBUFDS_DIFF_OUT_ INTERMDISABLE)
IBUFDS_DIFF_OUT_INTERMDISABLE
I
IB OB
O
UG471_c1_73_021214
IBUFDISABLE
INTERMDISABLE
X-Ref Target - Figure 1-2 4
Figure 1-24: Input/Output Buffer Primitive (IOBUF)
ug471_c1_20_041112
IOBUF
IO
to/from device pad
I (Input)
from FPGA
O (Output)
to FPGA
T
3-state input
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