Xilinx SelectIO 7 Series User Manual

128 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 2: SelectIO Logic Resources
OPPOSITE_EDGE Mode
In OPPOSITE_EDGE mode, both the edges of the clock (CLK) are used to capture the data
from the FPGA logic at twice the throughput. This structure is similar to the Virtex-6 FPGA
implementation. Both outputs are presented to the data input or 3-state control input of the
IOB. The timing diagram of the output DDR using the OPPOSITE_EDGE mode is shown
in Figure 2-18.
SAME_EDGE Mode
In SAME_EDGE mode, data can be presented to the IOB on the same clock edge.
Presenting the data to the IOB on the same clock edge avoids setup time violations and
allows the user to perform higher DDR frequency with minimal register to register delay,
as opposed to using the CLB registers. Figure 2-19 shows the timing diagram of the output
DDR using the SAME_EDGE mode.
Clock Forwarding
Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to
forward clocks from the FPGA logic to the output pins.
X-Ref Target - Figure 2-1 8
Figure 2-18: Output DDR Timing in OPPOSITE_EDGE Mode
ug471_c2_16_011811
CLK
OCE
OQ
D1
D2
D1A D2A D1B
D1A D1B D1C D1D
D2A D2B D2C D2D
D2B
D1C D2C D1D
X-Ref Target - Figure 2-1 9
Figure 2-19: Output DDR Timing in SAME_EDGE Mode
ug471_c2_17_011811
CLK
OCE
OQ
D1
D2
D1A D2A D1B
D1A D1B D1C D1D
D2A D2B D2C D2D
D2B
D1C D2C D1D
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Xilinx SelectIO 7 Series Specifications

General

FPGA Family	7 Series
Programmable Slew Rate	Yes
Programmable Output Strength	Yes
Hot Swap Capability	Yes
I/O Standard Support	LVCMOS, LVTTL, HSTL, SSTL
Programmable Termination	Yes
Configuration	JTAG, SPI
Input Delay Elements	Yes
Output Delay Elements	Yes
Differential Termination	Yes
Compatible Series	Virtex-7, Kintex-7, Artix-7
Maximum I/O Pins	Up to 1200+ (device dependent)

Summary

Preface

About This Guide

Provides an overview of the document's scope and content.

Guide Contents

Lists the chapters covered in the user guide.

Additional Resources

Points to further documentation and support resources.

Chapter 1: SelectIO Resources

I/O Tile Overview

Describes the basic structure and components of SelectIO I/O tiles.

SelectIO Resources General Guidelines

Summarizes general design rules for using SelectIO resources.

7 Series FPGA DCI—Only available in the HP I/O banks

Explains Digitally Controlled Impedance (DCI) and its availability in HP I/O banks.

Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM)

Details the uncalibrated split termination feature in HR I/O banks.

7 Series FPGA SelectIO Primitives

Introduces the various I/O buffer primitives available for SelectIO resources.

7 Series FPGA SelectIO Attributes/Constraints

Covers attributes and constraints for configuring SelectIO I/O features.

Supported I/O Standards and Terminations

Provides an overview of supported I/O standards and their termination options.

Rules for Combining I/O Standards in the Same Bank

Outlines rules for mixing different I/O standards within the same I/O bank.

Simultaneous Switching Outputs

Discusses analysis and mitigation of noise from simultaneous switching outputs (SSOs).

Pin Planning to Mitigate SSO Sensitivity

Offers guidance on pin planning to reduce sensitivity to SSO noise.

Chapter 2: SelectIO Logic Resources

ILOGIC Resources

Describes the input logic blocks (ILOGIC) for data capture and processing.

Input DDR Overview (IDDR)

Explains the Double Data Rate (DDR) input registers and their operational modes.

Input Delay Resources (IDELAY)

Details the programmable delay primitive (IDELAYE2) for fine-tuning input timing.

IDELAY Attributes

Lists and describes the attributes for configuring the IDELAY primitive.

IDELAY Modes

Explains the different operational modes for the IDELAY primitive.

IDELAYCTRL

Describes the IDELAYCTRL module for calibrating delay taps.

OLOGIC Resources

Describes the output logic blocks (OLOGIC) for data output and 3-state control.

Output DDR Overview (ODDR)

Explains the Double Data Rate (DDR) output registers and their operational modes.

Output Delay Resources (ODELAY)—Not Available in HR Banks

Details the programmable delay primitive (ODELAYE2) for output timing adjustment.

ODELAY Attributes

Lists and describes the attributes for configuring the ODELAY primitive.

ODELAY Modes

Explains the different operational modes for the ODELAY primitive.

Chapter 3: Advanced SelectIO Logic Resources

Input Serial-to-Parallel Logic Resources (ISERDESE2)

Introduces the ISERDESE2 for high-speed serial-to-parallel conversion.

ISERDESE2 Primitive (ISERDESE2)

Describes the ISERDESE2 primitive and its ports.

ISERDESE2 Attributes

Lists and describes the attributes for configuring the ISERDESE2.

ISERDESE2 Clocking Methods

Explains clocking arrangements for ISERDESE2 in different interface types.

ISERDESE2 Width Expansion

Details how to expand ISERDESE2 modules for wider parallel interfaces.

Bitslip Timing Model and Parameters

Explains the timing and operation of the Bitslip submodule.

Output Parallel-to-Serial Logic Resources (OSERDESE2)

Introduces the OSERDESE2 for high-speed parallel-to-serial conversion.

OSERDESE2 Primitive

Describes the OSERDESE2 primitive and its ports.

OSERDESE2 Attributes

Lists and describes the attributes for configuring the OSERDESE2.

OSERDESE2 Width Expansion

Details how to expand OSERDESE2 modules for wider parallel interfaces.

OSERDESE2 Latencies

Summarizes the latency values for OSERDESE2 based on data rate and width.

Timing Characteristics of 2:1 SDR Serialization

Illustrates the timing for 2:1 SDR serialization.

Timing Characteristics of 8:1 DDR Serialization

Illustrates the timing for 8:1 DDR serialization.

Timing Characteristics of 4:1 DDR 3-State Controller Serialization

Illustrates the timing for 4:1 DDR 3-state serialization.

IO_FIFO Overview

Provides an overview of the IO_FIFO resources for I/O data transfer.

IN_FIFO

Describes the IN_FIFO primitive and its modes of operation.

OUT_FIFO

Describes the OUT_FIFO primitive and its modes of operation.

Appendix A: Termination Options for SSO Noise Analysis

Default Terminations for SSN Noise Analysis by I/O Standard

Lists default off-chip termination options for SSN analysis.