7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 143
UG471 (v1.10) May 8, 2018
Chapter 3
Advanced SelectIO Logic Resources
Introduction
The I/O functionality in 7 series FPGAs is described in Chapter 1 through Chapter 3 of this
user guide.
• Chapter 1 covers the electrical characteristics of input receivers and output drivers,
and their compliance with many industry standards.
• Chapter 2 describes the register structures dedicated for sending and receiving SDR
or DDR data.
• This chapter covers additional resources:
• Input serial-to-parallel converters (ISERDESE2) and output parallel-to-serial
converters (OSERDESE2) support very fast I/O data rates, and allow the internal
logic to run up to 8 times slower than the I/O.
• The Bitslip submodule can re-align data to word boundaries, detected with the
help of a training pattern.
Input Serial-to-Parallel Logic Resources (ISERDESE2)
The ISERDESE2 in 7 series FPGAs is a dedicated serial-to-parallel converter with specific
clocking and logic features designed to facilitate the implementation of high-speed
source-synchronous applications. The ISERDESE2 avoids the additional timing
complexities encountered when designing deserializers in the FPGA fabric.
ISERDESE2 features include:
• Dedicated deserializer/serial-to-parallel converter
The ISERDESE2 deserializer enables high-speed data transfer without requiring the
FPGA fabric to match the input data frequency. This converter supports both single
data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel
converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the
serial-to-parallel converter creates a 4-, 6-, 8-bit wide parallel word mode when using
one ISERDESE2, and 10- or 14-bit-wide parallel word when using two cascaded
ISERDESE2.
• Bitslip submodule
The Bitslip submodule allows designers to reorder the sequence of the parallel data
stream going into the FPGA fabric. This can be used for training source-synchronous
interfaces that include a training pattern.
• Dedicated support for strobe-based memory interfaces
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