Xilinx SelectIO 7 Series User Manual

18 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Supply Voltages for the SelectIO Pins
V
CCO
The V
CCO
supply is the primary power supply of the 7 series I/O circuitry. The V
CCO (V)
columns in Table 1-55 provide the V
CCO
requirements for each of the supported I/O
standards, and illustrate the V
CCO
requirements for both inputs and outputs as well as the
optional internal differential termination circuit. All V
CCO
pins for a given I/O bank must
be connected to the same external voltage supply on the board, and as a result all of the
I/O within a given I/O bank must share the same V
CCO
level. The V
CCO
voltage must
match the requirements for the I/O standards that have been assigned to the I/O bank. An
incorrect V
CCO
voltage can result in loss of functionality or damage to the device. The
7 series power supply requirements, including power-on and power-off sequencing, are
described in the 7 series FPGA data sheets.
In HP I/O banks, if the I/O standard voltage requirement is <
1.8V, but a V
CCO
> 2.5V is
applied, the device automatically enters an overvoltage protection mode. Reconfiguring
the device with the correct V
CCO
level restores normal operation.
V
REF
Single-ended I/O standards with a differential input buffer require an input reference
voltage (V
REF
). When V
REF
is required within an I/O bank, the two multi-function V
REF
pins for the bank must be used as V
REF
supply inputs. 7 series FPGAs can optionally use an
internally generated reference voltage by enabling the INTERNAL_VREF constraint. For
more information on this constraint, see 7 Series FPGA SelectIO Attributes/Constraints,
page 46.
V
CCAUX
The global auxiliary (V
CCAUX
) supply rail is primarily used for providing power to the
various block feature’s interconnect logic inside the 7 series FPGAs. In the I/O banks,
V
CCAUX
is also used to power input buffer circuits for some of the I/O standards. These
include all of the single-ended I/O standards at or below 1.8V, and also some of the 2.5V
standards (HR I/O banks only). Additionally, the V
CCAUX
rail provides power to the
bank’s differential input buffer circuits used for the differential and V
REF
I/O standards.
The 7 series power supply requirements, including power-on and power-off sequencing,
are described in the 7 series FPGA data sheets.
V
CCAUX_IO
The auxiliary I/O (V
CCAUX_IO
) supply rail is only present in HP I/O banks and provides
power to the I/O circuitry. The Kintex-7 and Virtex-7 FPGAs data sheets contain a table
titled Maximum Physical Interface (PHY) Rate for Memory Interfaces that references
V
CCAUX_IO
. This table indicates how the V
CCAUX_IO
pins can be powered at either 1.8V
(default), or optionally at 2.0V to achieve higher frequency performance for certain types
of memory interfaces. Although this table is designed for memory interfaces, it can also
provide guidance on powering V
CCAUX_IO
for other high-speed single-ended interfaces
based on the target bit rates. The table does not apply to LVDS, which uses a different type
of driver circuit than the single-ended drivers that are more affected by the V
CCAUX_IO
level. Thus, for LVDS interfaces, it does not matter which voltage level the V
CCAUX_IO
rail
is powered at. The default value of 1.8V affords a lower-power consumption and provides
very close to the same performance in the I/Os. The 2.0V option is available when the
slightly-increased performance is required for the very fastest bit rates supported for the
single-ended drivers.
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English