56 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Table 1-14 details the allowed attributes that can be applied to the LVCMOS15 I/O
standard. This standard is available in both the HR and HP I/O banks.
Table 1-15 details the allowed attributes that can be applied to the LVCMOS12 I/O
standard. This standard is available in both the HR and HP I/O banks.
LVDCI (Low-Voltage Digitally Controlled Impedance)
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as
LVCMOS, must have a drive impedance that matches the characteristic impedance of the
driven line. The HP I/O banks in the 7 series devices provide a controlled impedance
output driver to provide series termination without external-source termination resistors.
The impedance is set by the common external reference resistors, with resistance equal to
the trace characteristic impedance, Z
0
.
Sample circuits illustrating both unidirectional and bidirectional topologies for a
controlled impedance driver are shown in Figure 1-41 and Figure 1-42. The DCI I/O
standards supporting a controlled impedance driver are: LVDCI_15 and LVDCI_18.
Table 1-14: Allowed Attributes for the LVCMOS15 I/O Standard
Attributes
Primitives
IBUF/IBUFG
OBUF/OBUFT/IOBUF
HP I/O Banks HR I/O Banks
IOSTANDARD LVCMOS15 LVCMOS15 LVCMOS15
DRIVE N/A 2, 4, 6, 8, 12, 16 4, 8, 12, 16
SLEW N/A {FAST, SLOW} {FAST, SLOW}
Table 1-15: Allowed Attributes for the LVCMOS12 I/O Standard
Attributes
Primitives
IBUF/IBUFG
OBUF/OBUFT/IOBUF
HP I/O Banks HR I/O Banks
IOSTANDARD LVCMOS12 LVCMOS12 LVCMOS12
DRIVE N/A 2, 4, 6, 8 4, 8, 12
SLEW N/A {FAST, SLOW} {FAST, SLOW}
Table 1-16: Available I/O Bank Type
HR HP
N/A Available
To Next Page
Loading...
