Xilinx SelectIO 7 Series - DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18; DIFF_HSTL_II_T_DCI and DIFF_HSTL_II_T_DCI_18; HSTL Class I (1.2 V, 1.5 V, or 1.8 V)

62 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
Differential HSTL can also be used for differential clock and DQS signals in memory
interface designs.
DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18
Differential HSTL class-II pairs complementary single-ended HSTL_II type drivers with a
differential receiver, including on-chip split-thevenin termination. Differential HSTL
class-II is intended to be used in bidirectional links. Differential HSTL can also be used for
differential clock and DQS signals in memory interface designs.
DIFF_HSTL_II_T_DCI and DIFF_HSTL_II_T_DCI_18
These standards are almost the same as the DIFF_HSTL_II_DCI and
DIFF_HSTL_II_DCI_18 standards except that the termination is only present when the
driver is 3-stated.
HSTL Class I (1.2V, 1.5V, or 1.8V)
Figure 1-46 shows a sample circuit illustrating a termination technique for HSTL class-I for
the 1.2V, 1.5V, or 1.8V versions. In a specific circuit, all drivers and receivers must be at the
same voltage level (either 1.2V, 1.5V or 1.8V); they are not interchangeable. Only HP I/O
banks support the DCI standards.
Table 1-28: Available I/O Bank Type
HR HP
N/A Available
Table 1-29: Available I/O Bank Type
HR HP
N/A Available
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