Xilinx SelectIO 7 Series - Timing Characteristics of 2:1 SDR Serialization

170 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 3: Advanced SelectIO Logic Resources
Timing Characteristics of 2:1 SDR Serialization
In Figure 3-16, the timing of a 2:1 SDR data serialization is illustrated.
Clock Event 1
On the rising edge of CLKDIV, the word AB is driven from the FPGA logic to the D1 and
D2 inputs of the OSERDESE2 (after some propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word AB is sampled into the OSERDESE2 from the D1
and D2 inputs.
Clock Event 3
The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDESE2. This
latency is consistent with the Table 3-11 listing of a 2:1 SDR mode OSERDESE2 latency of
one CLK cycle.
X-Ref Target - Figure 3-16
Figure 3-16: OSERDESE2 Data Flow and Latency in 2:1 SDR Mode
UG471_c3_16_111011
D2
BD
CLKDIV
CLK
ABCDEF
OQ
D1
AC
F
E
Clock
Event 1
Clock
Event 2
Clock
Event 3
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