Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 151
UG471 (v1.10) May 8, 2018
Input Serial-to-Parallel Logic Resources (ISERDESE2)
DATA_RATE Attribute
The DATA_RATE attribute defines whether the incoming data stream is processed as
single data rate (SDR) or double data rate (DDR). The allowed values for this attribute are
SDR and DDR. The default value is DDR.
DATA_WIDTH Attribute
The DATA_WIDTH attribute defines the parallel data output width of the serial-to-parallel
converter. The possible values for this attribute depend on the INTERFACE_TYPE and
DATA_RATE attributes. See Table 3-3 for supported data widths.
When the DATA_WIDTH is set to widths larger than eight, a pair of ISERDESE2 must be
configured into a master-slave configuration. See
ISERDESE2 Width Expansion. Width
expansion is not allowed in memory mode.
INTERFACE_TYPE Attribute
The INTERFACE_TYPE attribute determines whether the ISERDESE2 is configured in
memory or networking mode. The allowed values for this attribute are MEMORY,
MEMORY_DDR3, MEMORY_QDR, OVERSAMPLE, or NETWORKING. The default
mode is MEMORY.
Figure 3-5 illustrates the ISERDESE2 internal connections when in MEMORY mode.
SRVAL_Q2 Sets the value after reset of the second
sample register.
Binary: 0 or 1 1
SRVAL_Q3 Sets the value after reset of the third sample
register.
Binary: 0 or 1 1
SRVAL_Q4 Sets the value after reset of the fourth sample
register.
Binary: 0 or 1 1
IOBDELAY Sets whether an input delay applies to
registered and/or non-registered outputs.
See Using D and DDLY in the ISERDESE2.
NONE, IBUF, IFD, or BOTH NONE
Table 3-2: ISERDESE2 Attributes (Cont’d)
Attribute Name Description Value
Default
Value
Table 3-3: Supported Data Widths
INTERFACE_TYPE DATA_RATE Supported Data Widths
NETWORKING
SDR 2, 3, 4, 5, 6, 7, 8
DDR 4, 6, 8, 10, 14
MEMORY
MEMORY_DDR3
MEMORY_QDR
SDR None
DDR 4
Send Feedback

Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English