7 Series FPGAs SelectIO Resources User Guide www.xilinx.com UG471 (v1.10) May 8, 2018
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/2011 1.0 Initial Xilinx release.
04/06/2011 1.0.1 Updated disclaimer and copyright sections on page 2.
05/31/2011 1.1 Added New Features. Updated the example device including Figure 1-15 and the
partgen example on page 24. Added VRN/VRP External Resistance Design Migration
Guidelines.
Updated the BITSLIP Submodule section including Figure 3-12. Removed Figure 3-13:
Bits from Data Input Stream (D) of Figure 3-12.
07/20/2012 1.2 Updated paragraph before Table 1-1. Added LVDS signaling to Table 1-1. Updated
V
CCO
and V
CCAUX_IO
. Updated Xilinx DCI. Removed V
CCINT
. Added Match_cycle
Configuration Option, DCIUpdateMode Configuration Option, DCIRESET Primitive,
and Special DCI Requirements for Some Banks. Updated DCI Cascading. Updated DCI
cascading guidelines after Figure 1-7. Updated table note in Table 1-3. Added
Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM). Updated 7 Series
FPGA SelectIO Primitives. Added DCI_CASCADE Constraint and VCCAUX_IO
Constraint. Updated IBUF_LOW_PWR Attribute, Output Slew Rate Attributes, Output
Drive Strength Attributes, PULLUP/PULLDOWN/KEEPER Attribute for IBUF,
OBUFT, and IOBUF, and 7 Series FPGA I/O Resource VHDL/Verilog Examples. Put
Internal V
REF
inside Differential Termination Attribute, page 49. Updated DRIVE
attribute in Table 1-10. Updated titles of Figure 1-41 through Figure 1-44. Updated LVDS
and LVDS_25 (Low Voltage Differential Signaling), including adding Figure 1-72.
Added IN_TERM attribute to SSTL (Stub-Series Terminated Logic). Added table note to
Table 1-55. Added Simultaneous Switching Outputs.
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