7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 115
UG471 (v1.10) May 8, 2018
Input Delay Resources (IDELAY)
Note: The DDLY pin timing diagrams and parameters are identical to the D pin timing diagrams and
parameters.
Input Delay Resources (IDELAY)
Every I/O block contains a programmable delay primitive called IDELAYE2. The IDELAY
can be connected to an ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2 block.
IDELAYE2 is a 31-tap, wraparound, delay primitive with a calibrated tap resolution. Refer
to the 7 series FPGA data sheets for delay values. It can be applied to the combinatorial
input path, registered input path, or both. It can also be accessed directly from the FPGA
logic. IDELAY allows incoming signals to be delayed on an individual input pin basis. The
tap delay resolution is contiguously calibrated by the use of an IDELAYCTRL reference
clock from the range specified in the 7 series FPGA data sheets.
T
ICOCKD
/T
IOCKDD
DDLY pin Setup/Hold with respect to CLK
Combinatorial
T
IDI
D pin to O pin propagation delay, no Delay
Sequential Delays
T
IDLO
D pin to Q1 pin using flip-flop as a latch without Delay
T
ICKQ
CLK to Q outputs
T
RQ
S/R pin to OQ/TQ out
Table 2-3: ILOGIC Switching Characteristics (Cont’d)
Symbol Description
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