Xilinx SelectIO 7 Series User Manual

114 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 2: SelectIO Logic Resources
Clock Event 1
• At time T
ICE1CK
before Clock Event 1, the input clock enable signal becomes
valid-high at the CE1 input of both of the DDR input registers, enabling them for
incoming data. Since the CE1 and D signals are common to both DDR registers, care
must be taken to toggle these signals between the rising edges and falling edges of
CLK as well as meeting the register setup-time relative to both edges.
• At time T
IDOCK
before Clock Event 1 (rising edge of CLK), the input signal becomes
valid-high at the D input of both registers and is reflected on the Q1 output of
input-register 1 at time T
ICKQ
after Clock Event 1.
Clock Event 4
• At time T
IDOCK
before Clock Event 4 (falling edge of CLK), the input signal becomes
valid-low at the D input of both registers and is reflected on the Q2 output of
input-register 2 at time T
ICKQ
after Clock Event 4 (no change in this case).
Clock Event 9
•At time T
ISRCK
before Clock Event 9, the S/R signal (configured as synchronous reset
in this case) becomes valid-high resetting Q1 at time T
ICKQ
after Clock Event 9, and
Q2 at time T
ICKQ
after Clock Event 10.
Table 2-3 describes the timing parameters of the ILOGIC switching characteristics in the
7 series FPGA data sheets.
X-Ref Target - Figure 2-1 0
Figure 2-10: ILOGIC in IDDR Mode Timing Characteristics
(OPPOSITE_EDGE Mode)
Table 2-3: ILOGIC Switching Characteristics
Symbol Description
Setup/Hold
T
ICE1CK
/T
ICKCE1
CE1 pin Setup/Hold with respect to CLK
T
ISRCK
/T
ICKSR
S/R pin Setup/Hold with respect to CLK
T
IDOCK
/T
IOCKD
D pin Setup/Hold with respect to CLK
12345678 91011
T
IDOCK
T
ICE1CK
T
ISRCK
T
ICKQ
T
ICKQ
T
ICKQ
T
IDOCK
CLK
D
CE1
S/R
(Reset)
Q1
Q2
T
ICKQ
UG471_c2_08_081215
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English