20 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
impedance due to process variation. It also continuously adjusts the impedances to
compensate for variations of temperature and supply voltage fluctuations.
For the I/O standards with controlled impedance drivers, DCI controls the driver
impedance to either match the two reference resistors, or for some standards, to match half
the value of these reference resistors.
For the I/O standards with controlled parallel termination, DCI provides the parallel
termination for both transmitters and receivers. This eliminates the need for termination
resistors on the board, reduces board routing difficulties and component count, and
improves signal integrity by eliminating stub reflection. Stub reflection occurs when
termination resistors are located too far from the end of the transmission line. With DCI,
the termination resistors are as close as possible to the output driver or the input buffer,
thus, eliminating stub reflections. DCI is only available in 7 series FPGAs HP I/O banks.
DCI is not available in HR I/O banks.
Xilinx DCI
DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of
the driver or the parallel-termination value for all of the I/Os of that bank. The N reference
pin (VRN) must be pulled up to V
CCO
by a reference resistor, and the P reference pin (VRP)
must be pulled down to ground by another reference resistor. The value of each reference
resistor should be either equal to the characteristic impedance of the PC board traces or
twice that value.
To implement DCI in a design:
1. Assign one of the DCI I/O standards in an HP I/O bank (see Table 1-2 and Table 1-3).
2. Connect the VRN multi-function pin to a precision resistor tied to the V
CCO
rail for the
same bank.
3. Connect the VRP multi-function pin to a precision resistor tied to ground.
The following sections discuss how to determine the precision resistor values for VRN and
VRP for the different I/O standards. Only one set of VRN and VRP resistors is used for
each bank, so all DCI standards within each bank must be able to share the same external
resistance values. If several I/O banks in the same I/O bank column are using DCI, and all
of those I/O banks use the same VRN/VRP resistor values, the internal VRN and VRP
nodes can be cascaded so that only one pair of pins for all of the I/O banks in the entire I/
O column is required to be connected to precision resistors. This option is called DCI
cascading and is detailed in DCI Cascading, page 22. This section also describes how to
determine if I/O banks share the same I/O bank column. If DCI I/O standards are not
used in the bank, these pins are available as regular I/O pins. UG475
: 7 Series FPGAs
Packaging and Pinout Specifications gives detailed pin descriptions.
DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or
off. The impedance is adjusted to match the external reference resistors. The adjustment
starts during the device startup sequence. By default, the DONE pin does not go High until
the first part of the impedance adjustment process is completed.
The DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the
RST input to the DCIRESET primitive while the device is operating, resets the DCI state
machine and restarts the calibration process. All I/Os using DCI will be unavailable until
the LOCKED output from the DCIRESET block is asserted. This functionality is useful in
applications where the temperature and/or supply voltage changes significantly from
device power-up to the nominal operating condition.
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