60 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 1: SelectIO Resources
HSTL (High-Speed Transceiver Logic)
The high-speed transceiver logic (HSTL) standard is a general purpose high-speed bus
standard is defined by JEDEC (JESD8-6). The HSTL standards have four variations
(classes). To support clocking high-speed memory interfaces, differential versions are also
available. 7 series FPGA I/O supports class-I for the 1.2V version of HSTL (in HP banks),
and class-I and II for the 1.5V and 1.8V versions, including the differential versions. The
differential versions of the standard require a differential amplifier input buffer and a
push-pull output buffer. The HP I/O banks also support DCI versions.
HSTL_ I and HSTL_ I_18
HSTL_I and HSTL_ I_18 use V
CCO
/2 as a parallel-termination voltage (V
TT
) and are
intended for use in unidirectional links.
HSTL_I_12
HSTL_I_12 uses V
CCO
/2 as a parallel-termination voltage (V
TT
) and is intended for use in
unidirectional links.
HSTL_ I_DCI and HSTL_ I_DCI_18
HSTL_I_DCI and HSTL_I_DCI_18 provide on-chip split thevenin termination powered
from V
CCO
, creating an equivalent parallel-termination voltage (V
TT
) of V
CCO
/2, and are
intended for use in unidirectional links.
HSTL_ II and HSTL_ II_18
HSTL_II and HSTL_II_18 use V
CCO
/2 as a parallel-termination voltage (V
TT
) and are
intended for use in bidirectional links.
Table 1-19: Available I/O Bank Type
HR HP
Available Available
Table 1-20: Available I/O Bank Type
HR HP
N/A Available
Table 1-21: Available I/O Bank Type
HR HP
N/A Available
Table 1-22: Available I/O Bank Type
HR HP
Available Available
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