180 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 3: Advanced SelectIO Logic Resources
Resetting the IO_FIFO
An IO_ FIFO has a single asynchronous reset that is internally resynchronized with both
the read and write clock domains. To ensure proper reset, RESET must be asserted High for
at least four cycles of either RDCLK or WRCLK, whichever is slower, before writing to the
IO_FIFO. The RDEN and WREN must be held Low while RESET is asserted.
The IO_FIFOs should be held in reset until both the write and read clocks are present and
stable. Similarly, if the read or write clocks are not available until after configuration, the
IO_FIFO must be reset as described above after valid clocks are asserted.
EMPTY and FULL Flags
The FULL flag, when asserted High, signals that the FIFO core and the input register are
both full. The state of the output register is ignored.
The EMPTY flag indicates the status of the data in the output register. When the EMPTY
flag is asserted High, the data in the output register is not valid.
ALMOST EMPTY and ALMOST FULL Flags
The ALMOSTEMPTY and ALMOSTFULL flags provide an early indication that the
IO_FIFO is approaching its limits. The flags can be configured to assert one or two cycles
prior to the IO_FIFO reaching a full or empty state. A value of 1 indicates that there is only
one word remaining to read or write. A value of 2 indicates that two words are remaining
to read or write.
Due to the asynchronous nature of the IO_FIFO and internal synchronization, the flags
might be overly pessimistic. During a read operation, there might be more data stored than
is indicated by an ALMOSTEMPTY flag output of 1 or 2. During a write operation there
can be more space available to write than indicated by an ALMOSTFULL flag output of 1
or 2.
The ALMOSTEMPTY and ALMOSTFULL flags do not necessarily overlap with the FULL
and EMPTY flags. It is possible to have ALMOSTEMPTY assert and deassert before
EMPTY asserts. This will occur if WRCLK is more than two times faster than RDCLK.
Table 3-19 summarizes all the applicable IO_FIFO attributes.
Q5[7:4], Q6[7:4]
O
Supplemental data out ports Q10 and Q11. Used only in
4 x 4 mode. Data on these ports is sourced from the
corresponding input ports D5[7:4] and D6[7:4].
EMPTY
O
Empty flag. Synchronized to RDCLK.
FULL
O
Full flag. Synchronized to WRCLK.
ALMOSTEMPTY
(1)
O
Programmable level empty flag. Synchronized to RDCLK.
ALMOSTFULL
(1)
O
Programmable level full flag. Synchronized to WRCLK.
Notes:
1. The corresponding attribute can be set to a value of 1 or 2 (see Table 3-19, page 181). Accordingly, at
least one or two reads or writes occur after the flag asserts. Due to the asynchronous nature of the FIFO,
there can be one or two additional reads or writes increasing the total reads or writes to three or four.
Table 3-18: OUT_FIFO Ports (Cont’d)
Port Name Input/output Description
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