Xilinx SelectIO 7 Series - Page 179

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 179
UG471 (v1.10) May 8, 2018
IO_FIFO Overview
Table 3-18 lists the available ports in the OUT_FIFO primitive.
X-Ref Target - Figure 3-21
Figure 3-21: OUT_FIFO Primitive
Table 3-18: OUT_FIFO Ports
Port Name Input/output Description
RDCLK
I
Read clock. Connect to BUFR, BUFG, or BUFH.
WRCLK
I
Write clock. Connect to BUFR, BUFG, or BUFH.
RESET
I
Reset, active High. Clears counters, pointers, and data.
D0[7:0] – D9[7:0]
I
Ten 8-bit data in ports in 8 x 4 mode. Twelve 4-bit data in
ports in 4 x 4 mode. Connect to fabric if used for external
interfaces.
D5[7:4], D6[7:4]
I
Supplemental data in ports D10 and D11. Used only in 4 x 4
mode. Data on the ports appears on corresponding output
ports Q5[7:4] and Q6[7:4].
RDEN
I
Read enable.
WREN
I
Write enable.
Q0[3:0] – Q9[3:0]
O
Ten 4-bit data output buses. Connect to OLOGIC if used for
external interfaces.
D0[7:0]
EMPTY
D1[7:0]
D2[7:0]
D3[7:0]
D4[7:0]
D5[7:0]
D6[7:0]
D7[7:0]
D8[7:0]
D9[7:0]
RDEN
WREN
RDCLK
WRCLK
RESET
Q0[3:0]
Q1[3:0]
Q2[3:0]
Q3[3:0]
Q4[3:0]
Q5[7:0]
Q6[7:0]
Q7[3:0]
Q8[3:0]
Q9[3:0]
FULL
ALMOSTEMPTY
ALMOSTFULL
(1)
(1)
(1)
(1)
UG471_c3_21_111611
Notes:
1. Extra input ports D10 (D5[7:4]) and D11 (D6[7:4]) and output ports Q10 (Q5[7:4]) and
Q11 (Q5[7:4]) in 4 x 4 mode.
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