Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 81
UG471 (v1.10) May 8, 2018
Supported I/O Standards and Terminations
Figure 1-60 shows a sample circuit illustrating a termination technique for differential
SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional DCI termination. In a specific
circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or
1.2V); they are not interchangeable. Also shown in Figure 1-60, only SSTL18_II_DCI has
internal split-termination resistors present in an output pin.
X-Ref Target - Figure 1-60
Figure 1-60: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional DCI Termination
ug471_c1_50_121214
IOB
DIFF_SSTL18_(I/II)_DCI
DIFF_SSTL15_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
DIFF_SSTL18_(I/II)_DCI
DIFF_SSTL15_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
DIFF_SSTL18_(I/II)_DCI
DIFF_SSTL15_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
+
–
DCI
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
IOB
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
Z
0
Z
0
V
CCO
=
1.8V for DIFF_SSTL18_(I/II)_DCI
1.5V for DIFF_SSTL15_DCI
1.35V for DIFF_SSTL135_DCI
1.2V for DIFF_SSTL12_DCI
V
CCO
=
1.8V for DIFF_SSTL18_II_DCI
V
CCO
=
1.8V for DIFF_SSTL18_(I/II)_DCI
1.5V for DIFF_SSTL15_DCI
1.35V for DIFF_SSTL135_DCI
1.2V for DIFF_SSTL12_DCI
V
CCO
=
1.8V for DIFF_SSTL18_II_DCI
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English