Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 87
UG471 (v1.10) May 8, 2018
Supported I/O Standards and Terminations
Figure 1-67 shows a sample circuit illustrating a board topology (with no termination) for
differential HSUL_12 with unidirectional DCI signalling.
Figure 1-68 shows a sample circuit illustrating a board topology (with no termination) for
differential HSUL_12 with bidirectional signalling.
X-Ref Target - Figure 1-67
Figure 1-67: Differential HSUL_12 with Unidirectional DCI Signalling
ug471_c1_57_0111811
IOB
DIFF_HSUL_12_DCI
DIFF_HSUL_12_DCI
+
–
DCI
DIFF_HSUL_12_DCI
IOB
Z
0
Z
0
R
0
= 50Ω
R
0
= 50Ω
X-Ref Target - Figure 1-68
Figure 1-68: Differential HSUL_12 with Bidirectional Signalling
Z
0
IOB
IOB
DIFF_HSUL_12 DIFF_HSUL_12
+
–
External Termination
DIFF_HSUL_12
ug471_c1_58_011811
Z
0
DIFF_HSUL_12
DIFF_HSUL_12 DIFF_HSUL_12
+
–
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English