Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 133
UG471 (v1.10) May 8, 2018
OLOGIC Resources
Figure 2-24 illustrates IOB DDR 3-state register timing. This example is shown using DDR
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 2-7, page 111.
Clock Event 1
• At time T
OTCECK
before Clock Event 1, the 3-state clock enable signal becomes
valid-High at the TCE input of the 3-state ODDR register, enabling them for incoming
data. Care must be taken to toggle the TCE signal of the 3-state ODDR between the
rising edges and falling edges of CLK as well as meeting the register setup-time
relative to both clock edges.
• At time T
OTCK
before Clock Event 1 (rising edge of CLK), the 3-state signal T1
becomes valid-high at the T1 input of 3-state register and is reflected on the TQ output
at time T
OCKQ
after Clock Event 1.
Clock Event 2
• At time T
OTCK
before Clock Event 2 (falling edge of CLK), the 3-state signal T2
becomes valid-high at the T2 input of 3-state register and is reflected on the TQ output
at time T
OCKQ
after Clock Event 2 (no change at the TQ output in this case).
Clock Event 9
•At time T
OSRCK
before Clock Event 9 (rising edge of CLK), the S/R signal (configured
as synchronous reset in this case) becomes valid-high resetting 3-state Register,
reflected at the TQ output at time T
RQ
after Clock Event 9 (no change at the TQ output
in this case) and resetting 3-state Register, reflected at the TQ output at time T
RQ
after
Clock Event 10 (no change at the TQ output in this case).
X-Ref Target - Figure 2-2 4
Figure 2-24: OLOGIC ODDR 3-State Register Timing Characteristics
123 4567891011
T
OTCK
T
OTCECK
T
OTCK
T
OSRCK
T
RQ
CLK
T1
T2
TCE
S/R
TQ
T
OCKQ
ug471_c2_22_081215
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English