Xilinx SelectIO 7 Series - Page 184

184 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Appendix A: Termination Options for SSO Noise Analysis
LVCMOS (all voltages)
LVTTL (12 mA, 16 mA, and 24 mA drive)
Far V
TT
50Ω
MOBILE_DDR None
SSTL12 Far V
TT
50Ω
SSTL12_DCI Far V
TT
50Ω
SSTL12_T_DCI Far V
TT
50Ω
SSTL135 Far V
TT
50Ω
SSTL135_DCI Far V
TT
50Ω
SSTL135_R Far V
TT
50Ω
SSTL135_T_DCI Far V
TT
50Ω
SSTL15 Far V
TT
50Ω
SSTL15_DCI Far V
TT
50Ω
SSTL15_R Far V
TT
50Ω
SSTL15_T_DCI Far V
TT
50Ω
SSTL18_I Far V
TT
50Ω
SSTL18_I_DCI Far V
TT
50Ω
SSTL18_II Near V
TT
50Ω & Far V
TT
50Ω
SSTL18_II_DCI Far V
TT
50Ω
SSTL18_II_T_DCI Far V
TT
50Ω
BLVDS_25 Near Series 165Ω, Near Differential 140Ω, and
Far Differential 100Ω
HSLVDCI_15 None
HSLVDCI_18 None
LVDCI_15 None
LVDCI_18 None
LVDCI_DV2_15 None
LVDCI_DV2_18 None
LVDS Far Differential 100Ω
LVDS_25 Far Differential 100Ω
MINI_LVDS_25 Far Differential 100Ω
PCI33_3 None
PPDS_25 Far Differential 100Ω
RSDS_25 Far Differential 100Ω
Table A-1: Default Terminations for SSN Noise Analysis by I/O Standard (Cont’d)
IO Standard
(1)
Default Termination
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