Xilinx Alveo U50 User Manual

Card Features
The Alveo U50 accelerator card features are listed below. Detailed informaon for each feature is
provided in Chapter 4: Card Component Descripon.
• UltraScale+™ XCU50 FPGA
• Two 4 gigabyte (GB) HBM memory stacks (8 GB total)
○ 32 channels of 256 MB
Note: The xilinx_u50_xdma_201920_2 plaorm allows a maximum of 30 of the 32 available HBM
pseudo channels to be used. Using more will generate errors during hardware build. Xilinx
recommends using pseudo-channels 0:29 because pseudo channels 30 and 31 need to route across
fabric resources shared with the stac region possibly resulng in lower performance.
• One gigabit (Gb) quad SPI ash memory for conguraon
• Ethernet networking interfaces
○ Two SFP-DD connectors support 4x10/25 GbE (ES3 card)
○ One QSFP28 connector supporng 100 GbE, 40 GbE, or 4x10/25 GbE (PQ card)
• JTAG and UART access through the maintenance connector
• 16-lane integrated Endpoint block for PCI Express connecvity
○ Gen3 x16 supporng to x1, x2, x4, x8, x16 lane conguraons
○ Single or dual Gen4 x8
• I2C bus
• Status LEDs
• Power management with system management bus (SMBus) voltage, current, and temperature
monitoring
• 75W PCIe slot power only
Note: The Alveo U50 card has separate power rails for FPGA fabric and HBM memory. Developers must
ensure their designs do not draw too much power for each rail. More informaon can be found in the
Known Issues table of the Alveo U50 Data Center Accelerator Card Installaon Guide (UG1370).
Block Diagram
Block diagrams of the Alveo U50 card with two SFP-DD interfaces (ES3 card) and one QSFP
interface (PQ card) are shown in the following gures.
Chapter 1: Introduction
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 7
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English