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Xilinx Alveo U50 User Manual
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Figur
e 2:
Car
d Block Diagram with SFP-DD Interface
Xilinx
XCU50
QSPI
Satellite
Controller
HBM
4 GB
U50
GTY x4
EP GTY x16
Single QSPI
Config Flash
HBM
4 GB
UAR
T
PCIe
(Gen3 x16 or
two Gen4 x8)
SFP-DD
2x 25 Gb/s
SFP-DD
2x 25 Gb/s
SMBus
X22932-072919
Figur
e 3:
Car
d Block Diagram with QSFP Interface
Xilinx
XCU50
QSPI
Satellite
Controller
HBM
4 GB
U50
GTY x4
EP GTY x16
Single QSPI
Config Flash
HBM
4 GB
UAR
T
PCIe
(Gen3 x16 or
two Gen4 x8)
QSFP28
4 GTY
SMBus
100 GbE
40 GbE
4x 10 GbE
X22939-072919
Chapter 1:
Introduction
UG1371 (v1.2) December 18, 2019
www.xilinx.com
Alveo U50 Accelerator Card User Guide
8
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d
F
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e
d
b
a
c
k
7
9
Table of Contents
Revision History
2
Table of Contents
3
Chapter 1: Introduction
5
Card Features
7
Block Diagram
7
Design Flows
9
Chapter 2: Vivado Design Flow
10
Board Support Files for the Alveo U50 Card
10
Creating an RTL Project Based on the U50 Board File
11
Creating an MCS File and Programming the Alveo Card
12
Chapter 3: Card Installation and Configuration
14
Standard ESD Measures
14
Installing Alveo Data Center Accelerator Cards in Server Chassis
15
FPGA Configuration
15
Chapter 4: Card Component Description
16
Ultrascale+ FPGA
16
Quad SPI Flash Memory
16
Maintenance Connector Interface
17
PCI Express Endpoint
17
SFP-DD Module Connectors
18
I2C Bus
18
Status Leds
18
Card Power System
19
Appendix A: Xilinx Design Constraints (XDC) File
21
Appendix B: Regulatory and Compliance Information
22
Safety Compliance
22
EMC Compliance
22
CE Directives
23
CE Standards
23
Compliance Markings
24
Other Compliance Statements
24
Appendix C: Additional Resources and Legal Notices
28
Xilinx Resources
28
Documentation Navigator and Design Hubs
28
References
28
Please Read: Important Legal Notices
30
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Xilinx Alveo U50 Specifications
General
Brand
Xilinx
Model
Alveo U50
Category
Computer Hardware
Language
English
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