Xilinx Zynq-7000 Manual

XILINX CONFIDENTIAL — DISCLOSED UNDER NDA
Zynq-7000 EPP Technical Reference Manual www.xilinx.com 3
UG585 (DRAFT) February 15, 2012
Chapter 33
Device Security
33 Device Security
33.1 Introduction
The Zynq-7000 devices support the ability to perform a secure boot to load encrypted PS images and PL bitstreams.
33.1.1 Terminology
In order to reduce confusion, the following terminology will be used in this chapter:
Term
AES
Definition
Advanced Encryption Standard
First Stage Boot Loader
(FSBL)
Code for the ARM PS initial boot and configuration
Image
PS software, i.e. FSBL, software application, etc…
Bitstream
PL configuration file
Boot Image
File stored in external boot memory. Contains header information
used by the internal boot ROM to successfully load the FSBL. May
also contain multiple partitions containing additional PS images or
PL configuration bitstreams
Cipher Text
Encrypted text, data or file
Plain Text
Unencrypted text, data or file
PCAP
Processor Configuration Access Port
PCAP-ICAP
PCAP emulating ICAP
PCAP-SMAP
PCAP emulating SelectMAP configuration

Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V