Yamaha Loopfactory DX200 - DX200 Parameter Structure; Understanding Songs, Patterns, and Voices Hierarchy

12
DX200
●
HD6437043E00F (XS936A00) CPU PLG150-DX: IC2
PIN
NO.
NAME I/O FUNCTION
PIN
NO.
NAME I/O FUNCTION
1 /WRHH O HH write 73 D15 I/O
2 DACK0 O DMA transfer strobe 74 D14 I/O
Data bus
3 /WRHL O HL write 75 D13 I/O
4 /CASHH O HH Column address strobe 76 D12 I/O
5 PE15 I/O Port E 77 VCC I Power suppl
y
6 VSS I Ground 78 D11 I/O Data bus
7 A0 O 79 VSS I Ground
8A1 O 80D10I/O
9 A2 O Address bus 81 D9 I/O
10 A3 O 82 D8 I/O Data bus
11A4 O 83D7I/O
12 VCC I Power suppl
y
84 D6 I/O
13 A5 O Address bus 85 VCC I Power suppl
y
14 VSS I Ground 86 D5 I/O Data bus
15 A6 O 87 VSS I Ground
16A7 O 88D4I/O
17A8 O 89D3I/O
18 A9 O 90 D2 I/O Data bus
19 A10 O 91 D1 I/O
20 A11 O Address bus 92 D0 I/O
21 A12 O 93 VSS I Ground
22 A13 O 94 XTAL I Cr
y
stal oscillator
23 A14 O 95 MD3 I Mode select
24 A15 O 96 EXTAL I Cr
y
stal oscillator
25 A16 O 97 MD2 I Mode select
26 VCC I Power suppl
y
98 NMI - Non-maskable interrupt
27 A17 O Address bus 99 VCC I Power suppl
y
28 VSS I Ground 100 PA16 I/O Port A
29 /CASHL O HL Column address strobe 101 PA17 I/O Port A
30 PA19 I/O Port A 102 MD1 I Mode select
31 /RAS O Row address strobe 103 MD0 I Mode select
32 /CASL O Column address strobe
(
low
)
104 PLLVCC I PLL Power suppl
y
33 PA18 I/O Port A 105 PLLCAP I PLL capacitor
34 /CASH O Column address strobe
(
hi
g
h
)
106 PLLVSS I PLL Ground
35 VSS I Ground 107 PA15 I/O Port A
36 RDWR O DRAM read/write 108 /RES I Reset
37 A18 O 109 /DREQ0 I DMA transfer re
q
uest
38 A19 O Address bus 110 TIOC0B I/O
MTU input capture/output compare (ch 0)
39 A20 O 111 PE2 I/O Port E
40 VCC I Power suppl
y
112 VCC I Power suppl
y
41 A21 O Address bus 113 PE3 I/O
42 VSS I Ground 114 PE4 I/O
Port E
43 /RD O Read 115 PE5 I/O
44 /WDTOVF O Watch do
g
timer overflow 116 PE6 I/O
45 D31 I/O Data bus 117 VSS I Ground
46 D30 I/O Data bus 118 AN0 I
47 /WRH O Hi
g
h write 119 AN1 I Analo
g
input
48 /WRL O Low write 120 AN2 I
49 /CS1 O Chip select 121 AN3 I
50 /CS0 O Chip select 122 PF4 I/O Port F
51 /IRQ3 I Interrupt re
q
uest 123 PF5 I/O Port F
52 /IRQ2 I Interrupt re
q
uest 124 AVSS I Analo
g
g
round
53 /CS3 O Chip select 125 PF6 I/O Port F
54 /CS2 O Chip select 126 PF7 I/O Port F
55 VSS I Ground 127 AVREF I Analo
g
reference volta
g
e
56 D29 I/O 128 AVCC I Analo
g
power suppl
y
57 D28 I/O 129 VSS I Ground
58 D27 I/O Data bus 130 RxDO I Receive data
59 D26 I/O 131 TxDO O Transmit data
60 D25 I/O 132 /IRQ1 I Interrupt re
q
uest
61 VSS I Ground 133 RxD1 I Receive data
62 D24 I/O Data bus 134 PA4 I/O Port A
63 VCC I Power suppl
y
135 VCC I Power suppl
y
64 D23 I/O 136 SCK1 I/O Serial clock
65 D22 I/O 137 PE7 I/O
66 D21 I/O 138 PE8 I/O
Port E
67 D20 I/O Data bus 139 PE9 I/O
68 D19 I/O 140 PE10 I/O
69 D18 I/O 141 VSS I Ground
70 D17 I/O 142 TIOC3D I/O
MTU input capture/output compare (ch 3)
71 VSS I Ground 143 PE12 I/O Port E
72 D16 I/O Data bus 144 PE13 I/O Port E