Abatron BDI2000

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bdiGDB for BDI2000 (PowerPC 7440/7450/86xx) User Manual 44

Note about memory accesses via JTAG:

On MPC86xx targets, memory accesses are done via the so called "System Access Port" (SAP). The

SAP is like an additional bus master. You can access memory while the core(s) are running and

memory coherency is maintained because SAP accesses are snooped. This has the side effect that

for example cache lines are flushed when memory is accessed via the BDI. Debugging code where

data/stack is only present in the cache without real memory behind it becomes almost impossible.

The following Telnet sequence shows the effect on reading cached data via the BDI.

8641>dcache 0

W0 : 0_0010f000 VD 0010f000 0010f004 0010f008 0010f00c

0010f010 0010f014 0010f018 0010f01c

W1 : 0_0010b000 VD 0010b000 0010b004 0010b008 0010b00c

0010b010 0010b014 0010b018 0010b01c

W2 : 0_00111000 VD 00111000 00111004 00111008 0011100c

00111010 00111014 00111018 0011101c

W3 : 0_0010d000 VD 0010d000 0010d004 0010d008 0010d00c

0010d010 0010d014 0010d018 0010d01c

8641>md 0x00111000

0_00111000 : 00111000 00111004 00111008 0011100c ................

0_00111010 : 00111010 00111014 00111018 0011101c ................

.......

0_001110e0 : 001110e0 001110e4 001110e8 001110ec ................

0_001110f0 : 001110f0 001110f4 001110f8 001110fc ................