bdiGDB for BDI2000 (PowerPC 7440/7450/86xx) User Manual 43
© Copyright 1997-2015 by ABATRON AG Switzerland V 1.13
3.5 Dual-Core Support for MPC8641D
The bdiGDB system supports concurrent debugging of the two e600 cores present in the
MPC8641D. For every core you can start its own GDB session. The port numbers used to attach the
remote targets are 2001 and 2002. In the Telnet you switch between the cores with the command
"select {0 | 1}".
In the configuration file, simply begin the init list line with the appropriate core number. If there is no
#n in front of a line, the BDI assumes core #0.
[INIT]
; init core register
#0 WREG MSR 0x00001002 ;MSR : ME,RI
#0 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit
#0 WSPR 1017 0x00000000 ;L2CR: disable L2 cache
;
#1 WREG MSR 0x00001002 ;MSR : ME,RI
#1 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit
The BDI supports different startup modes. The startup mode is defined via an entry in the [TARGET]
section of the BDI configuration file. The second e600 core (core #1) is handled by the BDI only if
there is a second "mode" parameter present in the STARTUP line. Because after reset the second
core is disabled, the BDI writes to the MCMPCR and enables it in cases where HALT is selected as
startup mode for the second core. Following some examples:
STARTUP HALT HALT
The second core will be enabled via MCMPCR and both core are halted at the reset vector via an
IABR breakpoint.
STARTUP RUN RUN
Both core are let running after reset. You can halt them individually via the Telnet "halt" command.
The BDI does not write to MCMPCR. Halting the second core will only succeed if it has been enabled
form the code running on the first core. The init list is not processed in this case.
STARTUP STOP 4000 HALT
The second core will be enabled via MCMPCR and halted at the reset vector via an IABR breakpoint.
The first core is let running for 4 seconds and the halted.
STARTUP STOP 4000 STOP
Both core are let running after reset for 4 seconds and the halted. The BDI does not write to MCMP-
CR. Halting the second core will only succeed if it has been enabled form the code running on the
first core during this 4 second runtime. After halting, the init list is processed.
STARTUP HALT RUN
Useful if you want to debug boot code on core#0 but want to be able to access core#1 later. The BDI
does not write to MCMPCR in this case.
STARTUP RUN HALT
The first core is let running while the second core will be enabled via MCMPCR and halted at the
reset vector via an IABR breakpoint.
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