92
Scheme communication logic for residual
overcurrent protection (EFC)
Chapter 10
Verifying settings by secondary
injection
11. Switch on the fault current (110% of the setting) and wait long-
er than the set value tCoord.
No EFC--TRIP signal should appear.
12. Switch off the fault current and the polarising voltage.
13. Reset the EFC--BLOCK digital input.
15.1.2 Permissive scheme
Procedure
1. Inject the polarising voltage 3U0 to 5% of Ub and the phase
angle between voltage and current to 65°, the current lagging
the voltage.
2. Inject current (65° lagging the voltage) in one phase to about
110% of the setting operating current, and switch off the cur-
rent with the switch.
3. Switch on the fault current (110% of the setting) and wait long-
er than the set value tCoord.
No EFC--TRIP signal should appear, and the EFC--CS binary out-
put should be activated.
4. Switch off the fault current.
5. Activate the EFC--CR binary input.
6. Switch on the fault current (110% of the setting) and measure
the operating time of the EFC logic.
Use the EFC--TRIP signal from the configured binary output to
stop the timer.
7. Compare the measured time with the set value tCoord.
8. Activate the EFC--BLOCK digital input.
9. Switch on the fault current (110% of the setting) and wait long-
er than the set value tCoord.
No EFC--TRIP signal should appear.
10. Switch off the fault current and the polarising voltage.
11. Reset the EFC--CR binary input and the EFC--BLOCK digital
input.
15.2 Completing the test
Continue to test another function or complete the test by setting the test mode to off.
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