Test for fast fault clearing
• Connect the test set for the injection of three phase voltages and currents to the
appropriate terminals of the IED.
• Enable the fast fault clearance by setting FastOperation to TRUE, and also
connect the inputs BLKDLFLT to TRUE and FUSEFAIL to FALSE.
• Also assume circuit breaker is in closed position, that is CBCLOSED is high, prior
to fault occurrence.
• Create a single phase fault on phase L1 such that phase L1 voltage is lower than
UPhSel< times quadrature phase to phase voltage and set Tau to default value.
• Activate carrier receive CR signal.
• Check that TRIP, TRL1, ARST and ARSTL1 are generated with the conditions
described.
• Check that activated trip signals and start signals are blocked by enabling BLKTR
and BLKST.
• Check that all activated signals are disabled by BLOCK input.
• If required, perform creating faults on the remaining phases in the similar way.
Test of delayed fault clearing for single pole tripping
• Connect the test set for the injection of three phase voltages and currents to the
appropriate terminals of the IED.
• Enable the delayed fault clearance for single pole tripping by setting Del1phOp to
1Ph (On), Del3PhOp to FALSE (Off) and also connect the inputs BLKDLFLT and
FUSEFAIL to FALSE.
• Also assume circuit breaker is in closed position, that is input CBCLD is high,
prior to fault occurrence.
• Create a single phase fault on phase L1 such that phase L1 voltage is lower than
UPhSel< times quadrature phase to phase voltage and set Tau to default value and
also inject the residual current such that it exceeds set IN> value.
• Check that output TRIN is activated after a set delay of tResCurr if ResCurrOper
is set to high.
• Check that TRIP and TRL1 are generated with the conditions described after a
set delay time of t1Ph and the outputs ARST and ARSTL1 are also activated. .
• Check that activated trip signals and start signals are blocked by enabling BLKTR
and BLKST.
• Check that all activated signals are disabled by BLOCK input.
• If required, perform creating faults on the remaining phases in the similar way.
Test of delayed fault clearing for three pole tripping
• Connect the test set for the injection of three phase voltages and currents to the
appropriate terminals of the IED.
• Enable the delayed fault clearance for three pole tripping by setting Del3phOp to
TRUE (On), Del1PhOp to 3Ph (Off) and also connect the inputs BLKDLFLT and
FUSEFAIL to FALSE.
• Also assume circuit breaker is in closed position, that is, the input CBCLOSED is
high prior to fault occurrence.
1MRK 506 355-UEN A Section 10
Testing functionality by secondary injection
Line distance protection REL670 2.1 IEC 181
Commissioning manual
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