Best master clock algorithm
The best master clock algorithm compares data describing two clocks to determine
which data describes the better clock. This algorithm is used to determine which of the
described clocks in several announce messages received by the local clock port is the
best clock. It is also used to determine whether a newly discovered clock is better than
the local clock.
The comparison algorithm is based on pair-wise comparisons of attributes with the
following precedence.
• Priority 1
• Clock class
• Clock accuracy
• Clock stability
• Priority 2
• Clock identity: A tie-breaker based on unique identifiers
Transition between the “IEEE 1588 master” and the “IEEE 1588 slave” modes causes
a short period of 1...3 s during which the SMV sender sets smpSynch in the SMV frame
to "0: less than 4 µs synch accuracy" mode. This activates the TxTR WARNING output
in the SMV receiver for a period of 11...33 s. The duration depends on the time offset
between the previous and the new IEEE 1588 v2 master. The TxTR ALARM output
activates in the SMV receiver if transfer is made to a IEEE 1588 v2 master that has 100
ms or more offset compared to the previous master. The ALARM output stays on for a
period of 11...33 s.
Time synchronization monitoring values
The time synchronization monitoring values are found via menu path
Monitoring/IED status/Time synchronization.
Table 12: Time synchronization monitoring values
Description
Value
Sync source IEEE 1588 master
IEEE 1588 slave
Sync status Up
Down
Sync accuracy 0...26 bits
Sync accuracy indicates the synchronization accuracy in number of fractional bits.
Sync accuracy can be calculated from the number of bits according to a formula.
Synch accuracy
bits
_ =
−
2 seconds
GUID-58685882-9968-4558-AFCC-45F63F2FE02D V1 EN
(Equation 1)
1MRS757809 C Section 6
Process bus and IEEE 1588 time synchronization
REC615 and RER615 75
Engineering Guide
To Next Page
Loading...
