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1.3.2.2 Video Signal Termination Impedance:
The analog video signal termination shall be 75 ohm +/- 2%.
1.3.2.3 Synchronization (Sync) Signals:
The Horizontal Sync (HS) TTL signal is used to initiate the display of a horizontal line. HS may be either
active high or active low according to the timing. The Vertical Sync (VS) TTL signal is used to initiate the
display of a new frame. VS may be either active high or active low according to the timing.
1.3.2.4 Sync Signal Levels:
The monitor must accept sync signals from both 3.3 and 5 volt TTL logic families. The inputs shall sense a
logic 0 when the input is 0.8 volt or less and shall sense a logic 1 when the input is 2.0 volts or greater. In
addition to these level requirements, there shall also be a minimum of 0.3 volt hysteresis provided for
noise immunity (typically by using a Schmitt Trigger input). That is, the input level at which the monitor
actually detects a logic 0 shall be at least 0.3 volt lower than the level at which it actually detects a logic 1.
If the monitor sync processing circuits were designed with 3.3 volt logic family, then the sync inputs must
be 5 volt tolerant.
1.3.2.5 Sync Signal Loading:
TTL input loading shall be equivalent to one TTL input load. When logic 0 is asserted by a sync input,
the maximum current source from any single monitor sync input to the driver is 1.6 mA. When logic 1 is
asserted, the maximum current source from the driver to any single monitor sync input is 400 uA.
1.3.2.6 Abnormal Signal Immunity:
The monitor shall not be damaged by improper sync timing, pulse duration, absence of sync,
abnormal input signal amplitude, or any other anomalous behavior of a graphics card.
1.3.2.7 Digital TMDS Input (HDMI signal input):
These video inputs consist of TX0+/- to TX2+/- and CLK+/- signals, each with its own shielded twisted
pair. These video signals are digital levels. Each signal pair is terminated by a normal 100 ohms.
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