ADLINK Technology SMARC LEC-MTK-I1200 - Page 30

LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1
Page 30 copyright © 2023 ADLINK Technology Inc.
4.4.2.2 CSI1 (4 lanes)
Name
Pin #
Description
I/O
Type
I/O
Level
Power
Domain
PU / PD
Comments
CSI1_RX0+
CSI1_RX0-
CSI1_RX1+
CSI1_RX1-
CSI1_RX2+
CSI1_RX2-
CSI1_RX3+
CSI1_RX3-
P7
P8
P10
P11
P13
P14
P16
P17
CSI1 differential input
I LVDS D-PHY
/ I LVDS M-PHY
Runtime
CSI1_CK+
CSI1_CK-
P3
P4
CSI1 differential clock input (point to
point)
I LVDS D-PHY
Runtime
I2C_CAM1_DAT /
CSI1_TX-
S2
I2C data for serial camera data
support link or differential data lane
I/O OD CMOS
/ O LVDS M-
PHY
1.8V
Runtime
PU 2.2K
MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU
MIPI-CSI 3.0 uses CSI0_TX-, no PU required
I2C_CAM1_CK /
CSI1_TX+
S1
I2C clock for serial camera data
support link or differential data lane
O OD CMOS
/ O LVDS M-
PHY
1.8V
Runtime
PU 2.2K
MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU
MIPI-CSI 3.0 uses CSI0_TX+, no PU required
CAM1_PWR# /
GPIO1
P109
Camera 1 Power Enable, active low
output.
O CMOS
1.8V
Runtime
Shared with GPIO1
CAM1_RST# /
GPIO3
P111
Camera 1 reset, active low output
O CMOS
1.8V
Runtime
Shared with GPIO 3
CAM_MCK
S6
Master clock output
O CMOS
1.8V
Runtime
Note
: MediaTek has support for up to 3 cameras. The 3
rd
camera goes to a feature connector on the module as CSI2.