LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1
Page 32 copyright © 2023 ADLINK Technology Inc.
4.4.4 USB ports
The OTG port comes straight from SoC, other ports are derived from a USB3.1/2.0 SS hub ( SOC has 2x USB2.0, 1x USB3.1
Type
Level
Domain
PD
USB0-
P61
USB differential data pairs for port 0
USB
USB over-current sense for port 0
CMOS
Pulled low by Module OD driver to disable USB0 power.
Pulled low by Carrier OD driver to indicate over-current
USB port 0 host power detection,
when this port is used as a device.
VBUS 5V
5V
When this Port is used as a device it can be connected to a
USB client port VBUS pin
Input pin to announce OTG device
insertion on USB 2.0 port
Resistor value to ground according to USB specification
USB1-
P66
USB differential data pairs for port 1
USB
USB over-current sense for port 1
CMOS
Pulled low by Module OD driver to disable USB1 power.
Pulled low by Carrier OD driver to indicate over-current
USB2-
P70
USB differential data pairs for port 2
USB
USB2_SSRX-
S75
Receive signal differential pairs for
SuperSpeed on port 2
USB SS
DC blocking capacitors 100nF shall be placed on the Carrier
USB2_SSTX-
S72
Transmit signal differential pairs for
SuperSpeed on port 2
USB SS
DC blocking capacitors 100nF shall be placed on the Carrier
USB over-current sense for port 2
CMOS
Pulled low by Module OD driver to disable USB2 power.
Pulled low by Carrier OD driver to indicate over-current