Aim-TTI TG5011A - Page 96

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Standard Event Status and Standard Event Status Enable Registers
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Standard Event Status Register which correspond to bits set in the Standard
Event Status Enable Register will cause the ESB bit to be set in the Status Byte Register.
The Standard Event Status Register is read and cleared by the *ESR? command. The Standard
Event Status Enable register is set by the *ESE <nrf> command and read by the *ESE? command.
It is a bit field where each bit has the following significance.
Bit 7: Power On. Set when power is first applied to the instrument.
Bit 6: User Request (Not used).
Bit 5: Command Error. Set when a syntax type error is detected in a command from the bus.
The parser is reset and parsing continues at the next byte in the input stream
Bit 4: Execution Error. Set when an error is encountered while attempting to execute a
completely parsed command. The appropriate error number will be reported in the
Execution Error Register, see Error Messages section
Bit 3: Not used.
Bit 2: Query Error. Set when a query occurs. The appropriate error number will be reported in
the Query Error Register, see Query Error Register section.
Bit 1: Not used.
Bit 0: Operation Complete: Set in response to the ‘*OPC’ command.
Execution Error Register
This register contains a number representing the last error encountered over the current interface.
The Execution Error Register is read and cleared using the ‘EER?’ command. On power up this
register is set to 0 for all interface instances.
Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE STD. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request Enable
Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating a
Service Request on the bus.
The Status Byte Register is read either by the *STB? command, which will return MSS in bit 6, or by
a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the *SRE
<nrf> command and read by the *SRE? command.
Bit 7 -
Not used.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting
Service message and the Master Status Summary message. RQS is returned in
response to a Serial Poll and MSS is returned in response to the *STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a response
message formatted and ready to send to the controller. The bit will be cleared after the
Response Message Terminator has been sent.
Bit 3 -
Not used.
Bit 2 -
Not used.
Bit 1 -
Not used
Bit 0 -
Not used