Altera DE1-SoC - DE1-SoC I2 C Multiplexer Functionality

DE1-SOC COMPUTER SYSTEM WITH NIOS II For Quartus II 15.0
A fragment of C code that uses the audio port is shown in Figure 26. The code checks to see when the depth of either
the left or right Read FIFO has exceeded 75% full, and then moves the data from these FIFOs into a memory buffer.
This code is part of a larger program that is distributed as part of the Altera Monitor Program. The source code can
be found under the heading sample programs, and is identified by the name Media.
volatile int * audio_ptr = (int *) 0xFF203040; // audio port address
int fifospace, int buffer_index = 0;
int left_buffer[BUF_SIZE];
int right_buffer[BUF_SIZE];
. . .
fifospace = *(audio_ptr + 1); // read the audio port fifospace register
if ( (fifospace & 0x000000FF) > 96) // check RARC, for > 75% full
{
/* store data until the audio-in FIFO is empty or the memory buffer is full */
while ( (fifospace & 0x000000FF) && (buffer_index < BUF_SIZE) )
{
left_buffer[buffer_index] = *(audio_ptr + 2); //Leftdata
right_buffer[buffer_index] = *(audio_ptr + 3); //Rightdata
++buffer_index;
fifospace = *(audio_ptr + 1); // read the audio port fifospace register
}
}
. . .
Figure 26. An example of code that uses the audio port.
4.2 Video-out Port
The DE1-SoC Computer includes a video-out port with a VGA controller that can be connected to a standard VGA
monitor. The VGA controller supports a screen resolution of 640 × 480. The image that is displayed by the VGA
controller is derived from two sources: a pixel buffer, and a character buffer.
4.2.1 Pixel Buffer
The pixel buffer for the video-out port reads stored pixel values from a memory buffer for display by the VGA
controller. As illustrated in Figure 27, the memory buffer provides an image resolution of 320 × 240 pixels, with the
coordinate 0,0 being at the top-left corner of the image. Since the VGA controller supports the screen resolution of
640 × 480, each of the pixel values in the pixel buffer is replicated in both the x and y dimensions when it is being
displayed on the VGA screen.
Figure 28a shows that each pixel value is represented as a 16-bit halfword, with five bits for the blue and red
components, and six bits for green. As depicted in part b of Figure 28, pixels are addressed in the memory buffer by
using the combination of a base address and an x,y offset. In the DE1-SoC Computer the pixel buffer uses the base
address (08000000)
16
, which corresponds to the starting address of the FPGA on-chip memory. Using this scheme,
the pixel at location 0,0 has the address (08000000)
16
, the pixel 1,0 has the address base + (00000000 000000001 0)
2
32 Altera Corporation - University Program
2015