DE1-SOC COMPUTER SYSTEM WITH NIOS II For Quartus II 15.0
called Media that is distributed with the Altera Monitor Program.
volatile short * pixel_buffer = (short *) 0x08000000; // Pixel buffer
volatile char * character_buffer = (char *) 0x09000000; // Character buffer
int x1, int y1, int x2, int y2, short pixel_color;
int offset, row, col;
int x, int y, char * text_ptr;
. . .
/* Draw a box; assume that the coordinates are valid */
for (row = y1; row <= y2; row++)
for (col = x1; col <= x2; ++col)
{
offset = (row << 9) + col;
*(pixel_buffer + offset) = pixel_color; // compute halfword address, set pixel
}
/* Display a text string; assume that it fits on one line */
offset = (y << 7) + x;
while ( *(text_ptr) )
{
*(character_buffer + offset) = *(text_ptr); // write to the character buffer
++text_ptr;
++offset;
}
Figure 31. An example of code that uses the video-out port.
4.3 Video-in Port
The DE1-SoC Computer includes a video-in port for use with the composite video-in connector on the DE1-SoC
board. The video digital-to-analog converter (DAC) connected to this port is configured to support an NTSC video
source. The video-in port provides frames of video at a resolution of 320 x 240 pixels. These video frames can be
displayed on a VGA monitor by using the video-out port described in Section 4.2. The video-in port writes each
frame of the video-in data into the pixel buffer described in Section 4.2.1. The video-in port can be configured to
provide two types of images: either the “raw” image provided by the video DAC, or a version of this image in which
only “edges” that are detected in the image are drawn.
The video-in port has a programming interface that consists of two registers, as illustrated in Figure 32. The Control
register at the address 0xFF20306C is used to enable or disable the video input. If the EN bit in this register is set
to 0, then the video-in core does not store any data into the pixel buffer. Setting EN to 1 and then changing EN to 0
can be used to capture a still picture from the video-in port.
The register at address 0xFF203070 is used to enable or disable edge detection. Setting the E bit in this register
to 1 causes the input video to passed through hardware circuits that detect edges in the images. The image stored
in the pixel buffer will then consist of dark areas that are puctuated by lighter lines along the edges that have been
detected. Setting E = 0 causes a normal image to be stored into the pixel buffer.
36 Altera Corporation - University Program
2015
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