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AMD XILINX VEK280 - Page 19

AMD XILINX VEK280
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3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
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Callout NumberRef. Des. Function Default Schematic Page
3-4: PC4 can drive POR_B
5-6: FTDI can drive POR_B
Open: POR_B source not connected
5-6 open
4 J34 VCC Fuse programming enable
1-2: Fuse programming enabled
2-3: Fuse programming disabled
2-3 15
5 J37 JTAG source enable
1-2: JTAG sources disabled
2-3: JTAG sources enabled
2-3 20
6 J300 USB shield GND
1-2: USB connector DC grounded
2-3: USB connector no DC grounded
1-2 37
7 J60 PCIe PRSNT_B WIDTH SEL
1-2: x1
3-4: x4
5-6: x8
7-8: x16
1-2, 3-4, 5-
6, 7-8
40
8 J203 SYSCTLR POR_B supervisor enable
1-2: SYSCTLR POR_B supervisor
enabled
Open: SYSCTLR POR_B supervisor
disabled
1-2 77
9 J347 Fan type
1-2: System controller PWM
2-3: Versal device MIO PWM
1-2 50
10 J348 TACH type
1-2: System controller TACH
2-3: Versal device MIO TACH
1-2 50
11 J406 MIO37 selection
1-2: ZU4_TRIGGER
2-3: CANFD0_INH_B
1-2 10

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