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AMD XILINX VEK280 - Page 29

AMD XILINX VEK280
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3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
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Manufacturer: Micron
Part number: MT53E512M32D1ZW-046 WT:B (dual die LPDDR4 SDRAM)
Component description
16 Gb (512 Mb x 32)
1.1V 200-ball TFBGA
LPDDR4-2133
System Reset POR_B
[Figure 1, callout 2]
POR_B is the Versal device processor reset, which can be controlled by:
SYSCTLR (U125)
PC4 header (J36)
FTDI USB JTAG chip (U20)
The VEK280 board POR circuit is shown in the following figure. U235 allows
directional open drain level shifting for all of these masters, and J326 allows them
to be bused together if desired. The TPS389001 U10 supervisor chip holds POR_B
off until power is valid.
Figure: POR_B Reset Circuit

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