AMD XILINX VEK280 - Page 54

3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
54/78
XCVE2802
VDU PCIe
X1Y0
GTYP
(CPM5)
Quad
103
X0Y1
BB [RS]
CH0 PCIe
Lane11
CH1 PCIe
Lane10
CH2 PCIe
Lane9
CH3 PCIe
Lane8
REF0PCIe_CLK2
REF1[UNUSED]
VDU MRMAC
X0Y0
GTYP
(CPM5)
Quad
102
X0Y0
BA [RS]
CH0 PCIe
Lane15
CH1 PCIe
Lane14
CH2 PCIe
Lane13
CH3 PCIe
Lane12
REF0PCIe_CLK3
REF1[UNUSED]
VDU HDIO
Bank
401 AA
PMCDIO
Bank
503
LPDMIO
Bank
502
 VDU HDIO
Bank
400 AB
PMCMIO
Bank
501
PMCMIO/PMCDIO
Bank
500
