✎
✎
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160 single-ended or 80 differential user-defined signals
24 transceiver differential pairs
6 transceiver (GBTCLK) differential clocks
4 differential (CLK) clocks
1 differential (REFCLK) clock (both C2M and M2C pairs)
1 differential (SYNC) clock (both C2M and M2C pairs)
239 ground and 17 power connections
For more information about the VITA 57.4 FMC+ specification, see the VITA FMC
Marketing Alliance website.
HDMI
[Figure 1, callout 18]
The VEK280 has one HDMI™ 2.1 source and one HDMI 2.1 sink that are provided by
HDMI 2.1 compatible redrivers and miscellaneous control signals. A separate high
quality programmable clock is provided for driving this entire circuit to allow
flexibility and tuning.
Note: The first release of the EA VEK280 has an FRL data rate limit of 8 Gbps
/lane.
HDMI Video Input/Output
The VEK280 evaluation board generates HDMI video output using the TI TMDS1204
HDMI redriver chip. This video output is fed to a Molex HDMI™ 2.1 receptacle. The
board also accepts HDMI video input on another Molex HDMI2.1 receptacle to
another TI TMDS1204 HDMI™ redriver on the receiving.
Note: The TDMS1204 supports lane swapping. The transmit side takes
advantage of this for improved layout and needs to be configured appropriately. For
more information, see the TDMS1204 datasheet, section Swap (8.2.5 in SLLSF57 –
AUGUST 2022 datasheet revision) and VEK280 schematic page 44.
The TMDS1204 HDMI 2.1 redriver supports data rates up to 12 Gbps. It is
backwards compatible with HDMI 1.4b and HDMI 2.0b. The TMDS1204 can support
both three and four lane HDMI 2.1 FRL at 3, 6, 8, 10, and 12-Gbps.
More information on the TI TMDS1204 is available on the TI website.
Note: The first release of the EA VEK280 board has a FRL data rate limit of 8
Gbps / lane
The series capacitor-connected HDMI TX and RX data signals from TMDS1204 are
routed to the VE2802 GTYP Bank 204.
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