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Limit Event Status Registers 1 and 2 are read and cleared by the LSR1? and LSR2? commands
respectively. Limit Event Status Enable Registers 1 and 2 are set by the LSE1<nrf> and
LSE2<nrf> commands and read by the LSE1? and LSE2? commands respectively.
Limit Event Status Register 1
Set when an output 1 sense trip has occurred
Set when an output 1 thermal trip has occurred
Set when an output 1 over current trip has occurred
Set when an output 1 over voltage trip has occurred
Set when output 1 enters current limit (constant current mode)
Set when output 1 enters voltage limit (constant voltage mode)
Limit Event Status Register 2
Set when the Auxiliary output trip has occurred
Set when the Auxiliary output enters current limit
Set when an output 2 sense trip has occurred
Set when an output 2 thermal trip has occurred
Set when an output 2 over current trip has occurred
Set when an output 2 over voltage trip has occurred
Set when output 2 enters current limit (constant current mode)
Set when output 2 enters voltage limit (constant voltage mode)
Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request
Enable Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating
a Service Request on the bus.
The Status Byte Register is read either by the *STB? command, which will return MSS in bit 6, or
by a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the
*SRE <nrf> command and read by the *SRE? command.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting Service
message and the Master Status Summary message. RQS is returned in response to a
Serial Poll and MSS is returned in response to the *STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a response
message formatted and ready to send to the controller. The bit will be cleared after the
Response Message Terminator has been sent.
Bit 1 - LIM2. This will be set if any bits in Limit Event Status Register 2 are set and
corresponding bits are set in Limit Event Status Enable Register 2.
Bit 0 - LIM1. This will be set if any bits in Limit Event Status Register 1 are set and
corresponding bits are set in Limit Event Status Enable Register 1.
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